Earlier today, we reported that iPhone 5′s A6 system on a chip (SoC) contains 1GB RAM, twice that of the iPhone 4S.
But it looks like that’s not the only improvement, AnandTech have done some further digging and has found details about the memory interface, speed and bandwidth of the new platform.
Apple thankfully didn’t obscure the details of its A6 slide at the launch event, which gave us a Samsung part number: K3PE7E700F-XGC2. Through crafty navigation of Samsung’s product guide, Brian Klug got us the details. The K3P tells us we’re looking at a dual-channel LPDDR2 package with 32-bit channels. The E7E7 gives us the density of each of the two DRAM die (512MB per die, 1GB total). The final two characters in the part number give us the cycle time/data rate, which in this case is 1066MHz.
Roughly 33% more peak memory bandwidth than the iPhone 4S, which can definitely help feed the faster GPU and drive the higher resolution display. Many vendors have been shipping LPDDR2-1066 so there’s nothing too surprising here. There’s understandably less bandwidth than in the 3rd gen iPad of course as the display/GPU requirements aren’t nearly as high.
Folks at Mac Observer have used the data from AnandTech to create this chart, which shows us the maximum bandwidth utilization for each of the iOS devices.
The faster memory bandwidth allows iPhone 5′s processor to read and store data about 33 percent faster than predecessors.
The custom-designed CPU core and the 1GB RAM with 33% more bandwidth utilization than the iPhone 4S, helps Apple’s A6 chip deliver up to two times performance improvement over the A5 chip that powers iPhone 4S.
As you can see from the slide that Apple had shown at the media event on Wednesday, everything is going to be snappier on iPhone 5.
Image via The Verge
We can’t wait to get our hands on the new iPhone. What about you? Have you pre-ordered your iPhone 5?